Closed-Loop Edge Automation for High-Volume PCBA Manufacturing.
Test Edge is a deterministic, 5-layer factory automation architecture deployed directly on shop-floor Ubuntu Edge Nodes. It standardizes instrument hardware abstraction (user_defined_hw_measure), central OTA recipe distribution, multi-port parallel execution, predictive X-in-Y fixture maintenance, rework quarantine, and ISO-9001 RBAC governance.
user_defined_hw_measure() HALFactory Telemetry Dashboard
Throughput & Yield Trend
Yield by Test Platform
Platform-Specific Checks
Yield by Central Program
| Program | Runs | Pass | FPY% |
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Product Hierarchy
| Type | Gen | Sub-Ver | Runs | FPY% |
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Lot / Batch Traceability
| Lot ID | SKUs | Runs | Fail | FPY% | Gate |
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| Time | Serial / Port | Lot | Product | Platform/Stn | Program | Measurements | Status / Bin |
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Visual Factory Flow & Live Station Status Map
Filter by Product to see which stations are producing which product (`NVME`, `SSD`, `DDR`, `PC_MB`, `GPU_AI`, `WIFI`), along with Active Lot, Test Program, Loading %, and Technician.
Central Station-to-Program Assignment
Bind Recipe & Limits to Platform / Station
Active Station-to-Recipe & Product Assignment Matrix
| Platform | Station | Product | Assigned Recipe | Mode | Ports | Action |
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Multi-Port PCB Batch Execution & Live Progress Monitor
Test Program Creation Studio (OTPL / Free Python) & Visual Flowchart
Module A: Organize Test Node Types into a 2D Dictionary by (Test Platform × Product Type: NVME, SSD, DDR, PC_MB, GPU_AI, WIFI). Module B: Edit flow order (Up / Down / Delete / Duplicate / Merge to Subflow), assign Trigger Conditions (ON_PASS, ON_FAIL_RECOVERY, NESTED_SUBFLOW), and click any node in the Interactive Visual Flowchart to expand or edit.
Visualizes regular ON_PASS flow, ON_FAIL_RECOVERY branches, and expandable SUBFLOW blocks. Click any flowchart node or subflow below to edit its variables, trigger condition, and child steps directly.
Search All Registered Test Programs (OTPL & Python Recipes across NVME, SSD, DDR, PC_MB, GPU_AI, WIFI)
| Program ID | Platform | Format | SKU | Flow Nodes & Subflows | Stage | Action |
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Test Program Release Status (Code Review / Pilot / Deploy) & Feature Planning
Plan upcoming test capabilities, assign target Product Phase (ES / QS / MP), and track readiness.
| Feature ID | Planned Capability | Platform | Target SKU | Target Milestone | Owner | Status |
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Product Lifecycle Visualizer & Time-Mapped Test Programs
Tracks every Product Family from ES (Engineering Sample) → QS (Qualification Sample) → MP (Mass Production) with time-aligned Test Programs across all 4 Platforms.
TP-*-v1.x-ESTP-*-v2.x-QS / PILOTTP-*-v3.x/v4.x-MPTest Program Quality Performance (Cpk, Gage R&R, NTF & DPPM)
| Test Program ID | Platform | Sample Size | FPY % | Cpk Index | Gage R&R % | False Fail (NTF) | Avg Cycle vs SLA | Grade |
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Test Failure Mode & Fail Bin Code Manager
| Bin Code | Platform | Failure Mode | Bound Test | Cross-Station Action | Hits |
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Station Hardware Wear-Out Alerts (≥ X Fails in Last Y Tests)
Response Flowchart to Fix Hardware (By Fail Bin Code & X-in-Y Rule)
Interactive decision tree showing how a test failure maps to a Fail Bin Code, evaluates the X-in-Y wear-out rule, quarantines problem hardware, tags suspect PCBs for rework, and executes hardware repair.
Hardware Pending Fix: Decide Downtime → Fixing → Release Production
Manage worn or failing test stations/ports through 1) Scheduled Downtime (Quarantined), 2) Active Fixing & Spare Replacement, and 3) Golden-Unit Verification & Release to Production.
Test Hardware Inventory, Spare Stock & Health Status
Tracks active fixture modules, pogo sockets, probe pins, RF cables, and spare stock levels ready for Page 13 maintenance swaps.
| Part SKU | Component Name | Platform | Installed | Spare Stock | Min Safety | Status | Allocate |
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PCB Rework & Retest Queue (Failed Due to Problem Hardware)
Automatically captures finished PCBs that failed on a degraded station/port prior to a Hardware Wear-Out alert so operators can clean, rework, and retest them on a healthy station instead of scrapping good boards.
| PCB Serial Number | Lot / Batch | Product SKU | Failed Station / Port | Fail Bin | Root Cause | Rework / Retest Status | Action |
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Production Engineering Change Notice (ECN / PCN) Registry
| ISO Doc ID | Timestamp | Category | Target | Description & Rollback | Approved By |
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SOP Training Qualification & Scope Access Control Matrix
Requires each role (Technician, Test Engineer, Test Lead, Product Owner) to read, understand, and digitally sign their scope SOPs to unlock module access.
Automated Operations Report (Day / Week / Month)
Automatically compiles throughput, FPY %, top Fail Bins, hardware wear-out downtime events, and recovered rework PCBs by Day, Week, or Month.
OTPL Visualizer, Live .tpl Source Editor & Single-PCB Flow Simulator
Visualize and edit Advantest T2000 OTPL (Open Architecture Test System Test Programming Language) FlowItem nodes, edit variables, configure node characteristics (FAIL_STOP, EDC_LOG, CONTINUE_ON_FAIL, RETEST_1X), and push directly to Test Stations (Page 5).
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TP-FVT-NVME-v5.2.tpl
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